With the development of the semiconductor technology, the critical size of semiconductor devices has become very small, it is becoming more difficult to include more semiconductor devices in a two-dimensional packaging structure, therefore a three-dimensional packaging becomes an effective method for improving the integration density of chips. Current three dimensional packaging techniques include die stacking and package stacking based on gold wire bonding and three-dimensional stacking based on through silicon via (TSV). Amongst of them, the three dimensional stacking based on the TSV have three advantages. The first advantage is the high integration density. The second advantage is that it can significantly reduce the interconnection length, and can effectively solve a signal delay problem in existing two-dimensional system level chip (SOC) technique. The third advantage is that the TSV technique can integrate chips with different functions (such as radio frequency, random access memory, logic and MEMS, etc) to achieve multiple-functions of the packaged chip. Therefore, the three-dimensional stacking process using the TSV interconnection structure is becoming a more and more dominant integrated chip packaging technique.
However, existing methods for forming a TSV structure may often need a chemical mechanical polishing (CMP) process to back grind the silicon substrate. The CMP process may generate stress effect on the silicon substrate and, thus, the thickness of the silicon substrate after the back grinding process cannot be very small. For example, the thickness may be at least 200 μm. Therefore, the depth of the TSV may also be at least 200 μm, the process for forming the TSV structure become more complex, and the production cost is increased. The disclosed methods and systems are directed to solve one or more problems set forth above and other problems.